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[ak4627] ms1278-e-02 2012/03 - 1 - general description the ak4627 is a single chip audio codec that incl udes four adc channels a nd six dac channels. the converters are designed with enhanced dual bit arch itecture for the adc?s, and advanced multi-bit architecture for the dac, enabling very low noise performance. the ak4627 adc supports both single-ended and differential inputs and outputs. a wide range of applications can be realized, including home theater, pro audio and car audio. the ak4627 is available in a 48-pin lqfp package. features ? 4ch 24bit adc - 64x oversampling - sampling rate up to 96khz - linear phase digital anti-alias filter - single-ended / differential input - s/(n+d): 92db (single-ended, differential) - dynamic range, s/n: 102db (single-ended), 103db (differential) - digital hpf for offset cancellation - i/f format: msb justified, i 2 s or tdm ? 6ch 24bit dac - 128x oversampling - sampling rate up to 192khz - 24bit 8 times digital filter - single-ended outputs - on-chip switched-capacitor filter - s/(n+d): 90db - dynamic range, s/n: 106db - i/f format: msb justified, lsb justified(20bit,24bit), i 2 s or tdm - individual channel digital volume with 128 levels and 0.5db step - soft mute - de-emphasis for 32khz, 44.1khz and 48khz - zero detect function ? high jitter tolerance ? ttl level digital i/f ? 3-wire serial and i 2 c bus p i/f for mode setting ? master clock: 256fs, 384fs or 512fs for fs=32khz to 48khz 128fs, 192fs or 256fs for fs=64khz to 96khz 128fs for fs=120khz to 192khz ? power supply: 4.5 to 5.5v ? power supply for output buffer: 2.7 to 5.5v ? small 48pin lqfp high performance multi-channel audio codec ak4627
[ak4627] ms1278-e-02 2012/03 - 2 - block diagram audio i / f lpf dac datt lpf dac datt lpf dac datt lpf dac datt lout1 rout1 lout2 rout2 ak4627 adc hpf adc hpf lin1+/lin1 lrck bick sdti1 sdti2 sdti3 mcl k lrck bick sdin1 sdin2 sdin3 mclk lpf dac datt lpf dac datt lout3 rout3 adc hpf adc hpf sdto1 sdto1 sdto2 sdto2 lin1- rin1+/rin1 rin1- lin2+/lin2 lin2- rin2+/rin2 rin2- block diagram
[ak4627] ms1278-e-02 2012/03 - 3 - ordering guide AK4627VQ -40 +105 c 48pin lqfp(0.5mm pitch) akd4627 evaluation board for ak4627 pin layout vss2 37 lin1+/lin1 36 38 rin2+/rin2 39 lin2- 40 lin2+/lin2 41 rin1- 42 43 rin1+/rin1 44 lin1- 45 tst1 46 sgl 47 a vdd 35 34 33 32 31 30 29 28 27 26 1 cad1 2 ps 3 sdto1 4 sdto2 5 tvdd 6 dvdd 7 vss1 8 tdm0/sda/cdti 9 dif1/scl/cclk 10 dif0/csn 11 23 22 21 20 19 18 17 16 15 14 13 lrck bick mclk top view dzfe 48 pdn 12 24 25 smute rin2- ak4627 sdti2 sdti1 tst3 sdti3 i2c/tst6 dfs0 tst2 tst4 tst5 lout1 rout2 lout2 rout3 lout3 dzf2 dzf1 vrefh vcom rout1 cad0
[ak4627] ms1278-e-02 2012/03 - 4 - pin/function no. pin name i/o function 1 cad0 i chip address 0 pin 2 cad1 i chip address 1 pin 3 ps i parallel/serial select pin ?l?: serial control mode, ?h?: parallel control mode 4 sdto1 o adc1 audio serial data output pin 5 sdto2 o adc2 audio serial data output pin 6 tvdd - output buffer power supply pin, 2.7v 5.5v 7 dvdd - digital power supply pin, 4.5v 5.5v 8 vss1 - digital ground pin, 0v tdm0 i tdm i/f format mode pin in parallel control mode ?l?: normal mode, ?h?: tdm mode 9 sda/cdti i/o control data input pin in serial control mode i2c pin= ?l?: cdti (3-wire se rial), i2c pin= ?h?: sda (i 2 c bus) dif1 i audio data interface format 1 pin in parallel control mode 10 scl/cclk i control data clock pin in serial control mode i2c pin= ?l?: cclk (3-wire serial), i2c pin= ?h?: scl (i 2 c bus) dif0 i audio data interface format 0 pin in parallel control mode 11 csn i chip select pin in 3- wire serial control mode this pin should be co nnected to dvdd at i 2 c bus control mode 12 pdn i power-down & reset pin when ?l?, the ak4627 is powered-down and the control registers are reset to default state. if the state of ps pin or cad1-0 pins change, then the ak4627 must be reset by the pdn pin. 13 mclk i master clock input pin 14 bick i audio serial data clock pin 15 lrck i input channel clock pin 16 sdti1 i dac1 audio serial data input pin 17 sdti2 i dac2 audio serial data input pin 18 sdti3 i dac3 audio serial data input pin 19 tst3 i test pin this pin should be connected to vss1 20 dfs0 i double speed sampling mode pin ( note 1 ) ?l?: normal speed, ?h?: double speed i2c i control mode select pin (ps pin = ?l?) ?l?: 3-wire serial, ?h?: i 2 c bus 21 tst6 i test pin (ps pin = ?h?) this pin should be connected to vss1 22 tst2 test pin this pin should be connected to vss1. 23 tst4 test pin this pin should be open. 24 tst5 test pin this pin should be open. 25 lout3 o dac3 lch analog output pin 26 rout3 o dac3 rch analog output pin 27 lout2 o dac2 lch analog output pin 28 rout2 o dac2 rch analog output pin 29 lout1 o dac1 lch analog output pin 30 rout1 o dac1 rch analog output pin
[ak4627] ms1278-e-02 2012/03 - 5 - no. pin name i/o function 31 vcom o common voltage output pin, avdd/2 large external capacitor around 2.2 f is used to reduce power-supply noise. 32 vrefh i positive voltage reference input pin, avdd 33 avdd - analog power supply pin, 4.5v 5.5v 34 vss2 - analog ground pin, 0v 35 dzf1 o zero input detect 1 pin ( note 2 ) when the input data of the group 1 follow total 8192 lrck cycles with ?0? input data, this pin goes to ?h?. and when rstn bit is ?0?, pwdan pin is ?l?, this pin goes to ?h?. it always is in ?l? when the ps pin is ?h?. 36 dzf2 o zero input detect 2 pin ( note 2 ) when the input data of the group 1 follow total 8192 lrck cycles with ?0? input data, this pin goes to ?h?. and when rstn bit is ?0?, pwdan pin is ?l?, this pin goes to ?h?. it always is in ?l? when the ps pin is ?h?. 37 rin2- i adc2 rch analog negative input pin (sgl pin = ?l?) rin2+ i adc2 rch analog positive input pin (sgl pin = ?l?) 38 rin2 i adc2 rch analog input pin (sgl pin = ?h?) 39 lin2- i adc2 lch analog negative input pin (sgl pin = ?l?) lin2+ adc2 lch analog positive input pin (sgl pin = ?l?) 40 lin2 i adc2 lch analog input pin (sgl pin = ?h?) 41 rin1- i adc1 rch analog negative input pin (sgl pin = ?l?) rin1+ i adc1 rch analog positive input pin (sgl pin = ?l?) 42 rin1 i adc1 rch analog input pin (sgl pin = ?h?) 43 lin1- i adc1 lch analog negative input pin (sgl pin = ?l?) lin1+ i adc1 lch analog positive input pin (sgl pin = ?l?) 44 lin1 i adc1 lch analog input pin (sgl pin = ?h?) 45 tst1 i test pin this pin should be connected to vss1. 46 sgl i single-ended input mode select pin. ?l?: adc differential input mode ?h?: adc single-ended input mode 47 dzfe i zero input detect enable pin ?l?: mode 7 (disable) at parallel mode, zero detect mode is selectable by dzfm3-0 bits at serial mode ?h?: mode 0 (dzf1 is and of all six channels) 48 smute i soft mute pin ( note 1 ) when this pin goes to ?h?, soft mute cycle is initialized. when returning to ?l?, the output mute releases. note 1. smute and dfs0 pins are ored with register data when the ps pin= ?l?. note 2. the output pin (dzf1 and dzf2) of zero detection results of each lineout channels can be selected by dzfm3-0 bits when the ps pin and dzfe pin= ?l?. ( table 11 ) note 3. all digital input pins except for pull-down should not be left floating.
[ak4627] ms1278-e-02 2012/03 - 6 - absolute maximum ratings (vss1=vss2=0v; note 4 ) parameter symbol min max unit power supplies analog digital output buffer avdd dvdd tvdd -0.3 -0.3 -0.3 6.0 6.0 6.0 v v v input current (any pins except for supplies) iin - 10 ma analog input voltage vina -0.3 avdd+0.3 v digital input voltage vind -0.3 dvdd+0.3 v ambient temperature (power applied) ( note 6 ) ta -40 105 c storage temperature tstg -65 150 c note 4. all voltages with respect to ground. note 5. vss1 and vss2 must be conn ected to the same analog ground plane. note 6. in case that pcb wiring density is 100% or more. warning: operation at or beyond these limits may result in permanent damage to the device. normal operation is not guaranteed at these extremes. recommended operating conditions (vss1=vss2=0v; note 4 ) parameter symbol min typ max unit power supplies ( note 7 ) analog digital output buffer avdd dvdd tvdd 4.5 4.5 2.7 5.0 5.0 5.0 5.5 5.5 5.5 v v v note 4. all voltages with respect to ground. note 7. the power up sequence between avdd, dvdd and tvdd is not critical. do not turn off only the ak4627 under the condition that a surrounding device is powered on and the i 2 c bus is in use. warning: akm assumes no responsibility for the usage beyond the conditions in this datasheet.
[ak4627] ms1278-e-02 2012/03 - 7 - analog characteristics (ta=25 c; avdd=dvdd=tvdd=5v; vss1=vss2=0v; vrefh=avdd; fs=48khz; bick=64fs; signal frequency=1khz; 24bit data; measurement frequency=20hz 20khz at 48khz, 20hz~40khz at fs=96khz, 20hz~40khz at fs=192khz; unless otherwise specified) parameter min typ max unit adc analog input characteristics (single-ended inputs) resolution 24 bits s/(n+d) (-0.5dbfs) fs=48khz fs=96khz 84 - 96 92 db db dr (-60dbfs) fs=48khz, a-weighted fs=96khz fs=96khz, a-weighted 94 88 93 102 99 105 db db db s/n ( note 11 ) fs=48khz, a-weighted fs=96khz fs=96khz, a-weighted 94 88 93 102 99 105 db db db interchannel isolation 90 110 db dc accuracy (single-ended inputs) interchannel gain mismatch 0.2 0.3 db gain drift 20 - ppm/ c input voltage ain=0.68xvrefh 3.2 3.4 3.6 vpp fs=48khz 10 14 k input resistance fs=96khz 11 k power supply rejection ( note 9 ) 50 db adc analog input characteri stics (differential inputs) 84 96 db s/(n+d) (-0.5dbfs) fs=48khz fs=96khz - 94 db 95 103 db 89 100 db dr (-60dbfs) fs=48khz, a-weighted fs=96khz fs=96khz, a-weighted 94 106 db 95 103 db 89 100 db s/n ( note 11 ) fs=48khz, a-weighted fs=96khz fs=96khz, a-weighted 94 106 db interchannel isolation 90 110 db dc accuracy (dif ferential inputs) interchannel gain mismatch 0.2 0.3 db gain drift 20 - ppm/ c input voltage ain=0.68xvrefh ( note 8 ) 3.2 3.4 3.6 vpp fs=48khz 22 32 k ? input resistance fs=96khz 19 k ? power supply rejection ( note 9 ) 50 - db common mode rejection ratio (cmrr) ( note 10 ) 60 db
[ak4627] ms1278-e-02 2012/03 - 8 - dac analog output characteristics resolution 24 bits s/(n+d) (0dbfs) fs=48khz fs=96khz fs=192khz 80 78 - 98 98 98 db db db dr (-60dbfs) fs=48khz, a-weighted fs=96khz fs=96khz, a-weighted fs=192khz fs=192khz, a-weighted 95 88 94 - - 106 100 106 100 106 db db db db db s/n ( note 12 ) fs=48khz, a-weighted fs=96khz fs=96khz, a-weighted fs=192khz fs=192khz, a-weighted 95 88 94 - - 106 100 106 100 106 db db db db db interchannel isolation 90 110 db dc accuracy interchannel gain mismatch 0.2 0.5 db gain drift 20 - ppm/ c output voltage aout=0.6xvrefh 2.75 3.0 3.25 vpp load resistance 5 k load capacitance 25 pf power supply rejection ( note 10 ) 50 db note 8. (lin+) ? (lin-) or (rin+) ? (rin-) ; this value is proportional to vrefh voltage. note 9. psr is applied to avdd, dvdd and tvdd with 1khz, 50mvpp. vrefh pin is held +5v. note 10. vrefh is held +5v, the input bias voltage is set to avdd1, avdd2 x 0.5. the 1khz, 1.52vpp signal is applied to lin- and lin+ with same phase (e.g. shorted) or rin- and rin+. the cmrr is measured as the attenuation level from 1.52vpp = -7dbfs. note 11. s/n measured by ccir-arm is 98db(@fs=48khz). note 12. s/n measured by ccir-arm is 102db(@fs=48khz). parameter min typ max unit power supplies power supply current (avdd+dvdd+tvdd) normal operation (pdn = ?h?) avdd fs=48khz, 96khz fs=192khz dvdd+tvdd fs=48khz ( note 13 ) fs=96khz fs=192khz power-down mode (pdn = ?l?) ( note 14 ) 57 34 19 27 27 80 86 51 29 40 40 200 ma ma ma ma ma a note 13. tvdd=0.1ma(typ). note 14. in the power-down mode. all digital input pins including clock pins (mclk, bick, lrck) are held vss1.
[ak4627] ms1278-e-02 2012/03 - 9 - filter characteristics (ta=25 c; avdd=dvdd=4.5 5.5v; tvdd=2.7 5.5v; fs=48khz) parameter symbol min typ max unit adc digital filter (decimation lpf): passband ( note 15 ) 0.1db -0.2db -3.0db pb 0 - - 20.0 23.0 18.9 - - khz khz khz stopband sb 28 khz passband ripple pr 0.04 db stopband attenuation sa 68 db group delay ( note 16 ) gd 16 1/fs group delay distortion gd 0 s adc digital filter (hpf): frequency response ( note 15 ) -3db -0.1db fr 1.0 6.5 hz hz dac digital filter: passband ( note 15 ) -0.1db -6.0db pb 0 - 24.0 21.8 - khz khz stopband sb 26.2 khz passband ripple pr 0.02 db stopband attenuation sa 54 db group delay ( note 16 ) gd 19.2 1/fs dac digital filter + analog filter: frequency response: 0 20.0khz 40.0khz ( note 17 ) 80.0khz ( note 17 ) fr fr fr 0.2 0.3 1.0 db db db note 15. the passband and stopband frequencies scale with fs. for example, 21.8khz at ?0.1db is 0.454 x fs. note 16. the calculating delay time which occurred by digital f iltering. this time is from setting the input of analog signal to setting the 24bit data of both channels to the output register for adc. for dac, this time is from setting the 20/24bit data of bo th channels on input register to the output of analog signal. note 17. 40.0khz; fs=96khz , 80.0khz; fs=192khz. dc characteristics (ta=25 c; avdd=dvdd=4.5 5.5v; tvdd=2.7 5.5v) parameter symbol min typ max unit high-level input voltage low-level input voltage vih vil 2.2 - - - - 0.8 v v high-level output voltage (sdto1-2 pins: iout=-100 a) (dzf1, dzf2 pins: iout=-100 a) low-level output voltage (sdto1-2, dzf1, dzf2 pins: iout= 100 a) (sda pin: iout= 3ma) voh voh vol vol tvdd-0.5 avdd-0.5 - - - - - - - - 0.5 0.4 v v v v input leakage current iin - - 10 a
[ak4627] ms1278-e-02 2012/03 - 10 - switching characteristics (ta=25 c; avdd=dvdd=4.5 5.5v; tvdd=2.7 5.5v; c l =20pf) parameter symbol min typ max unit master clock timing 256fsn, 128fsd: pulse width low pulse width high 384fsn, 192fsd: pulse width low pulse width high 512fsn, 256fsd, 128fsq: pulse width low pulse width high fclk tclkl tclkh fclk tclkl tclkh fclk tclkl tclkh 8.192 27 27 12.288 20 20 16.384 15 15 12.288 18.432 24.576 mhz ns ns mhz ns ns mhz ns ns lrck timing normal mode (tdm0= ?0?, tdm1= ?0?) normal speed mode double speed mode quad speed mode duty cycle fsn fsd fsq duty 32 64 128 45 48 96 192 55 khz khz khz % tdm256 mode (tdm0= ?1?, tdm1= ?0?) lrck frequency ?h? time ?l? time fsn tlrh tlrl 32 1/256fs 1/256fs 48 khz ns ns tdm128 mode (tdm0= ?1?, tdm1= ?1?) lrck frequency ?h? time ?l? time fsn tlrh tlrl 64 1/128fs 1/128fs 96 khz ns ns audio interface timing normal mode (tdm0= ?0?, tdm1= ?0?) bick period bick pulse width low pulse width high lrck edge to bick ? ? ( note 18 ) bick ? ? to lrck edge ( note 18 ) lrck to sdto(msb) bick ? ? to sdto1-2 sdti1-3 hold time sdti1-3 setup time tbck tbckl tbckh tlrb tblr tlrs tbsd tsdh tsds 81 32 32 20 20 20 20 40 40 ns ns ns ns ns ns ns ns ns ns tdm256 mode (tdm0= ?1?, tdm1= ?0?) bick period bick pulse width low pulse width high lrck edge to bick ? ? ( note 18 ) bick ? ? to lrck edge ( note 18 ) bick ? ? to sdto1 sdti1 hold time sdti1 setup time tbck tbckl tbckh tlrb tblr tbsd tsdh tsds 81 32 32 20 20 10 10 20 ns ns ns ns ns ns ns ns ns tdm128 mode (tdm0= ?1?, tdm1= ?1?) bick period bick pulse width low pulse width high lrck edge to bick ? ? ( note 18 ) bick ? ? to lrck edge ( note 18 ) bick ? ? to sdto1 sdti1-2 hold time sdti1-2 setup time tbck tbckl tbckh tlrb tblr tbsd tsdh tsds 81 32 32 20 20 10 10 20 ns ns ns ns ns ns ns ns ns note 18. bick rising edge must not occur at the same time as lrck edge.
[ak4627] ms1278-e-02 2012/03 - 11 - parameter symbol min typ max unit control interface timing (3-wire serial mode): cclk period cclk pulse width low pulse width high cdti setup time cdti hold time csn ?h? time csn ? ? to cclk ? ? cclk ? ? to csn ? ? tcck tcckl tcckh tcds tcdh tcsw tcss tcsh 200 80 80 40 40 150 50 50 ns ns ns ns ns ns ns ns control interface timing (i 2 c bus mode): scl clock frequency bus free time between transmissions start condition hold time (prior to first clock pulse) clock low time clock high time setup time for repeated start condition sda hold time from scl falling ( note 19 ) sda setup time from scl rising rise time of both sda and scl lines fall time of both sda and scl lines setup time for stop condition pulse width of spike noise suppressed by input filter capacitive load on bus fscl tbuf thd:sta tlow thigh tsu:sta thd:dat tsu:dat tr tf tsu:sto tsp cb - 1.3 0.6 1.3 0.6 0.6 0 0.1 - - 0.6 0 - 400 - - - - - - - 1.0 0.3 - 50 400 khz s s s s s s s s s s ns pf power-down & reset timing pdn pulse width ( note 20 ) pdn ? ? to sdto1-2 valid ( note 21 ) tpd tpdv 150 522 ns 1/fs note 19. data must be held for sufficient time to bridge the 300 ns transition time of scl. note 20. the ak4627 can be reset by bringing the pdn pin ?l? to ?h? upon power-up. note 21. these cycles are the number of lrck rising from the pdn pin rising edge. note 22. i 2 c-bus is a trademark of nxp b.v.
[ak4627] ms1278-e-02 2012/03 - 12 - timing diagram 1/fclk tclkl vih tclkh mclk vil 1/fsn, 1/fsd lrck vih vil tbck tbckl vih tbckh bick vil clock timing (tdm0 bit= ?0?) 1/fclk tclkl vih tclkh mclk vil 1/fs lrck vih vil tlrl tlrh tbck tbckl vih tbckh bick vil clock timing (tdm0 bit= ?1?)
[ak4627] ms1278-e-02 2012/03 - 13 - tlrb lrck vih bick vil tlrs sdto 50%tvdd tbsd vih vil tblr tsds sdti vih vil tsdh audio interface timing (tdm0 bit= ?0?) tlrb lrck vih bick vil sdto 50%tvdd tbsd vih vil tblr tsds sdti vih vil tsdh audio interface timing (tdm0 bit= ?1?)
[ak4627] ms1278-e-02 2012/03 - 14 - tcss csn vih cclk vil vih cdti vil vih vil c1 c0 r/w a4 tcckl tcckh tcds tcdh write command input timing (3-wire serial mode) csn vih cclk vil vih cdti vil vih vil d3 d2 d1 d0 tcsw tcsh write data input timing (3-wire serial mode) thigh scl sda vih tlow tbuf thd:sta tr tf thd:dat tsu:dat tsu:sta stop start start stop tsu:sto vil vih vil tsp i 2 c bus mode timing tpd vil pdn tpdv sdto 50%tvdd vih power-down & reset timing
[ak4627] ms1278-e-02 2012/03 - 15 - operation overview system clock the external clocks, which are required to operate th e ak4627, are mclk, lrck and bick. mclk should be synchronized with lrck but the phase is not critical. there are two methods to se t mclk frequency. in manual setting mode (acks bit= ?0?: default), the sampling speed is set by dfs0 and dfs1 bits ( table 1 ). the frequency of mclk at each sampling speed is set automatically. ( table 2 , table 3 , table 4 ). in auto setting mode (acks bit= ?1?), as mclk frequency is detected automatically ( table 5 ) and the internal master clock b ecomes the appropriate frequency ( table 6 ), it is not necessary to set dfs bits. the ak4627 is automatically placed in power saving mode when mclk or l rck is stopped during normal operation mode, and the analog output goes to vcom (typ). when mclk and lrck are input again, the ak4627 is powered up. after exiting reset following power-up, the ak4627 is not fully operational until mclk and lrck are input. dfs1 dfs0 sampling speed (fs) 0 0 normal speed mode 32khz~48khz (default) 0 1 double speed mode 64khz~96khz 1 0 quad speed mode 120khz~192khz table 1. sampling speed (manual setting mode) lrck mclk (mhz) bick (mhz) fs 256fs 384fs 512fs 64fs 32.0khz 8.1920 12.2880 16.3840 2.0480 44.1khz 11.2896 16.9344 22.5792 2.8224 48.0khz 12.2880 18.4320 24.5760 3.0720 table 2. system clock example (normal speed mode @manual setting mode) lrck mclk (mhz) bick (mhz) fs 128fs 192fs 256fs 64fs 88.2khz 11.2896 16.9344 22.5792 5.6448 96.0khz 12.2880 18.4320 24.5760 6.1440 table 3. system clock example (double speed mode @manual setting mode) (note: at double speed mode(dfs1 b it= ?0?, dfs0 bit= ?1?), 128fs an d 192fs are not available for adc.) lrck mclk (mhz) bick (mhz) fs 128fs 192fs 256fs 64fs 176.4khz 22.5792 - - 11.2896 192.0khz 24.5760 - - 12.2880 table 4. system clock example (quad speed mode @manual setting mode) (note: at quad speed mode(d fs1bit= ?1?, dfs0 bit= ?0?) are not available for adc.)
[ak4627] ms1278-e-02 2012/03 - 16 - mclk sampling speed 512fs normal 256fs double 128fs quad table 5. sampling speed (auto setting mode) lrck mclk (mhz) fs 128fs 256fs 512fs sampling speed 32.0khz - - 16.3840 44.1khz - - 22.5792 48.0khz - - 24.5760 normal 88.2khz - 22.5792 - 96.0khz - 24.5760 - double 176.4khz 22.5792 - - 192.0khz 24.5760 - - quad table 6. system clock example (auto setting mode) differential/single-ended input selection the ak4627 supports differential inputs ( figure 1 ) by setting the sgl pin = ?l?, and single-ended inputs ( figure 2 ) by setting the sgl pin= ?h?. when single-ended input mode, l/rin1-2 pins should be open, because l/rin1-2 pins output an invert signal of the input signal. the ak4627 includes an anti-aliasing filter (rc filter) for both differential input and the single-ended input. scf l/rin+ l/rin- lpf lpf ak4627 figure 1. differential input (sgl pin = ?l?) scf l/rin l/rin- lpf ak4627 (open) figure 2. single-ended input (sgl pin = ?h?)
[ak4627] ms1278-e-02 2012/03 - 17 - de-emphasis filter the ak4627 includes the digital de-emphasis filter (tc=50/15s) by iir filter. de-emphasis filter is not available in double speed mode and quad speed mode. this filter corr esponds to three sampling frequencies (32khz, 44.1khz, 48khz). de-emphasis of each dac can be set individually by register data of dema1-c0 (dac1: dema1-0, dac2: demb1-0, dac3: demc1-0, see ?register definitions?). mode sampling speed dem1 dem0 dem 0 normal speed 0 0 44.1khz 1 normal speed 0 1 off 2 normal speed 1 0 48khz 3 normal speed 1 1 32khz (default) table 7. de-emphasis control digital high pass filter the adc has a digital high pass filter for dc offset cancellation. the cut-off frequency of the hpf is 1.0hz at fs=48khz and scales with sampling rate (fs).
[ak4627] ms1278-e-02 2012/03 - 18 - audio serial interface format when tdm1 bit = ?0? and tdm0 pin = ?l? or when tdm1-0 bits = ?00?, four modes can be selected by the dif1-0 bits as shown in table 8 . in all modes the serial data is msb-first, 2?s complement format. the sdto1-2 are clocked out on the falling edge of bick and the sdti1-3 ar e latched on the rising edge of bick. mode 2, 3, 6, 7, 10, 11 in sdti input formats can be used for 16-20bit data by zeroing the unused lsbs. lrck bick mode tdm 1 tdm0 dif1 dif0 sdto1-2 sdti1-3 0 0 0 0 0 24bit, left justified 20bit, right justified h/l i 48fs i 1 0 0 0 1 24bit, left justified 24bit, right justified h/l i 48fs i 2 0 0 1 0 24bit, left justified 24bit, left justified h/l i 48fs i (default) 3 0 0 1 1 24bit, i 2 s 24bit, i 2 s l/h i 48fs i table 8. audio data formats (normal mode) the audio serial interface format becomes the tdm mode when the tdm0 pin is set to ?h?. the serial data of all adc (four channels) are output from the sdto1 pin and the sdto2 pin outputs ?l?. in the tdm256 mode, the serial data of all dac (six channels) are input to the sdti1 pin. the input data to sdti2-3 pins are ignored. bick should be fixed to 256fs. ?h? time and ?l? time of lrck should be 1/256fs at least. four modes can be selected by dif1-0 bits as shown in table 9 . in all modes the serial data is msb-first, 2?s comple ment format. the sdto1 is clocked out on the falling edge of bick and the sdti1 is latched on the rising edge of bick. loop1-0 bits should be set to ?0? at the tdm mode. tdm128 mode can be set by tdm1 bit as show in table 10 . in double speed mode, the serial data of dac (four channels; l1, r1, l2, r2) is input to the sdti1 pin. other two data (l3 and r3) are input to the sdti2 pin. the tdm0 pin (or tdm0 register) should be set to ?h? (or ?1?) if tdm256 mode is selected. the tdm0 register and tdm1 register should be set to ?1? if double speed mode is selected in tdm128 mode. lrck bick mode tdm 1 tdm0 dif1 dif0 sdto1 sdti1 i/o i/o 4 0 1 0 0 24bit, left justified 20bit, right justified i 256fs i 5 0 1 0 1 24bit, left justified 24bit, right justified i 256fs i 6 0 1 1 0 24bit, left justified 24bit, left justified i 256fs i 7 0 1 1 1 24bit, i 2 s 24bit, i 2 s i 256fs i table 9. audio data formats (tdm256 mode) lrck bick mode tdm 1 tdm0 dif1 dif0 sdto1 sdti1, sdti2 i/o i/o 8 1 1 0 0 24bit, left justified 20bit, right justified i 128fs i 9 1 1 0 1 24bit, left justified 24bit, right justified i 128fs i 10 1 1 1 0 24bit, left justified 24bit, left justified i 128fs i 11 1 1 1 1 24bit, i 2 s 24bit, i 2 s i 128fs i table 10. audio data formats (tdm128 mode)
[ak4627] ms1278-e-02 2012/03 - 19 - lrck bick ( 64fs ) sdto ( o ) 0 1 2 12 13 14 24 25 31 0 1 2 12 13 14 24 25 31 0 23 1 22 0 23 22 12 11 10 0 23 sdti ( i ) 1 18 0 19 8 7 1 18 0 19 8 7 lch data rch data don?t care don?t care 12 11 10 sdto-23:msb, 0:lsb; sdti-19:msb, 0:lsb figure 3. mode 0 timing lrck bick ( 64fs ) sdto ( o ) 0 1 2 8 9 10 24 25 31 0 1 2 8 9 10 24 25 31 0 23 1 22 0 23 22 16 15 14 0 23 sdti ( i ) 1 22 0 23 8 7 1 22 0 23 8 7 23:msb, 0:lsb lch data rch data don?t care don?t care 16 15 14 figure 4. mode 1 timing lrck bick ( 64fs ) sdto ( o ) 0 1 2 21 22 23 24 31 0 1 2 0 23 1 22 1 23 22 23 sdti ( i ) 22 23 0 22 23 23:msb, 0:lsb lch data rch data don?t care 2 2 1 28 29 30 23 0 22 23 24 31 1 0 don?t care 2 21 28 29 30 0 figure 5. mode 2 timing lrck bick ( 64fs ) sdto ( o ) 0 1 2 3 22 23 24 25 0 0 1 sdti ( i ) 31 29 30 23 22 1 22 23 0 23:msb, 0:lsb lch data rch data don?t care 2 2 1 0 2 3 22 23 24 25 0 31 29 30 23 22 1 22 23 0 don?t care 2 21 0 1 figure 6. mode 3 timing
[ak4627] ms1278-e-02 2012/03 - 20 - 256 bick bick(256fs) sdto1(o) sdti1(i) 22 0 l1 32 bick 18 0 l1 32 bick 18 0 r1 32 bic k 18 0 l2 32 bick 18 0 r2 32 bic k 18 0 l3 32 bick 18 0 r3 32 bic k 22 0 r1 32 bic k 22 23 19 19 19 19 19 23 19 23 19 lrck 22 0 l2 22 0 r2 23 23 32 bick 32 bick figure 7. mode 4 timing 256 bick bick(256fs) sdto1(o) sdti1(i) 22 0 l1 32 bick 22 0 l1 32 bick 22 0 r1 32 bic k 22 0 l2 32 bick 22 0 r2 32 bic k 22 0 l3 32 bick 22 0 r3 32 bic k 22 0 r1 32 bic k 22 23 23 23 23 23 23 23 23 23 23 lrck 22 0 l2 32 bick 22 0 r2 32 bic k 23 23 figure 8. mode 5 timing 256 bick bick(256fs) sdto1(o) sdti1(i) 22 0 l1 32 bick 22 0 l1 32 bick 22 0 r1 32 bic k 22 0 l2 32 bick 22 0 r2 32 bic k 22 0 l3 32 bick 22 0 r3 32 bic k 22 0 r1 32 bic k 22 22 23 23 23 23 23 23 23 23 23 23 lrck 22 0 l2 32 bick 22 0 r2 32 bic k 23 23 figure 9. mode 6 timing 256 bick bick(256fs) sdto1(o) sdti1(i) 23 0 l1 32 bick 23 0 l1 32 bick 23 0 r1 32 bic k 23 0 l2 32 bick 23 0 r2 32 bic k 23 0 l3 32 bick 23 0 r3 32 bic k 23 0 r1 32 bic k 23 23 lrck 23 0 l2 32 bick 23 0 r2 32 bick figure 10. mode 7 timing
[ak4627] ms1278-e-02 2012/03 - 21 - 128 bick bick(128fs) sdto1(o) 22 0 l1 32 bick l1 32 bick r1 32 bick l2 32 bick r2 32 bick l3 32 bick r3 32 bick 22 0 r1 32 bick 22 23 23 23 sdti1(i) 18 0 18 0 18 0 18 0 19 19 19 19 19 lrck sdti2(i) 18 0 18 0 19 19 19 22 0 l2 32 bick 22 0 r2 32 bick 23 23 figure 11. mode 8 timing 128 bick bick(128fs) 22 0 l1 32 bick l1 32 bick r1 32 bick l2 32 bick r2 32 bick l3 32 bick r3 32 bick 22 0 r1 32 bick 22 23 23 23 sdti1(i) 22 0 22 0 22 0 22 0 23 23 23 23 19 lrck sdti2(i) 22 0 22 0 23 23 19 22 0 l2 32 bick 22 0 r2 32 bick 23 23 sdto1(o) figure 12. mode 9 timing 128 bick bick(128fs) sdto1(o) 22 0 l1 32 bick l1 32 bick r1 32 bick l2 32 bick r2 32 bick l3 32 bick r3 32 bick 22 0 r1 32 bick 22 23 23 23 lrck sdti1(i) 22 0 22 0 22 0 22 0 23 23 23 23 22 23 sdti2(i) 22 0 22 0 23 23 22 23 22 0 l2 32 bick 22 0 r2 32 bic k 23 23 figure 13. mode 10 timing
[ak4627] ms1278-e-02 2012/03 - 22 - 128 bick bick(128fs) sdto1(o) 22 0 l1 32 bick l1 32 bick r1 32 bick l2 32 bick r2 32 bick l3 32 bick r3 32 bick 22 0 r1 32 bick 23 23 23 sdti1(i) 22 0 22 0 22 0 22 0 23 23 23 23 23 sdti2(i) 22 0 22 0 23 23 23 lrck 22 0 l2 22 0 r2 23 23 figure 14. mode 11 timing
[ak4627] ms1278-e-02 2012/03 - 23 - zero detection the ak4627 has two pins for zero detect flag outputs. the output pin (dzf1 and dzf2 pins) for zero detection results of each lineout channels can be selected by dzfm3- 0 bits when the ps pin and dzfe pin = ?l? ( table 11 ). zero detection mode is set to mode 0 when the dzfe pin= ?h? regardless of the ps pin. the dzf1 pin outputs and result of all six channels and the dzf2 pin is disabled (?l?) at mode 0. when the input data of all lineout channels of dzf1 (dzf2) pin are continuously zeros for 8192 lrck cycles, the dzf1 (dzf2) pin becomes ?h?. the dzf1 (dzf2) pin immediately returns to ?l? if input data of any channel of dzf1 (dzf2) pin is not zero. dzfm aout mode 3 2 1 0 l1 r1 l2 r2 l3 r3 0 0 0 0 0 dzf1 dzf1 dzf1 dzf1 dzf1 dzf1 1 0 0 0 1 dzf1 dzf1 dzf1 dzf1 dzf1 dzf2 2 0 0 1 0 dzf1 dzf1 dzf1 dzf1 dzf2 dzf2 3 0 0 1 1 dzf1 dzf1 dzf1 dzf2 dzf2 dzf2 4 0 1 0 0 dzf1 dzf1 dzf2 dzf2 dzf2 dzf2 5 0 1 0 1 dzf1 dzf2 dzf2 dzf2 dzf2 dzf2 6 0 1 1 0 dzf2 dzf2 dzf2 dzf2 dzf2 dzf2 7 0 1 1 1 disable (dzf1=dzf2 = ?l?) 8 1 0 0 0 dzf1 dzf1 dzf1 dzf1 dzf1 dzf1 9 1 0 0 1 dzf1 dzf1 dzf1 dzf1 dzf1 dzf1 10 1 0 1 0 11 1 0 1 1 12 1 1 0 0 13 1 1 0 1 14 1 1 1 0 15 1 1 1 1 disable (dzf1=dzf2 = ?l?) (default) table 11. zero detect control
[ak4627] ms1278-e-02 2012/03 - 24 - digital attenuator the ak4627 has channel-independent digital attenuator (128 levels, 0.5db step). attenuation level of each channel can be set by each att7-0 bits ( table 12 ). att7-0 attenuation level 00h 0db 01h -0.5db 02h -1.0db : : 7dh -62.5db 7eh -63db 7fh mute (- ) : feh mute (- ) ffh mute (- ) (default) table 12. attenuation level of digital attenuator transition time between set values of att7-0 bits can be selected by ats1-0 bits ( table 13 ). transition between set values is soft transition. ther efore, the switching noise does not occur in the transition. mode ats1 ats0 att speed 0 0 0 1792/fs 1 0 1 896/fs 2 1 0 256/fs 3 1 1 256/fs (default) table 13. transition time between set values of att7-0 bits the transition between set values is soft transition of 1792 levels in mode 0. it takes 1792/fs (37.3ms@fs=48khz) from 00h(0db) to 7fh(mute). when the pdn pin becomes ?l?, the atts are initialized to 00h. the atts are 00h when rstn bit= ?0?. when rstn bit return to ?1 ?, the atts fade to their current value. note: the attenuation level is calculated in 11bit accuracy.
[ak4627] ms1278-e-02 2012/03 - 25 - soft mute operation soft mute operation is performed at digital domain. when the smute pin changes to ?h?, the output signal is attenuated by - during att_data att transition time ( table 13 ) from the current att level. when the smute pin returns to ?l?, the mute is cancelled and the output attenuation gradually changes to the att level during att_data att transition time. if the soft mute is cancelled before attenuating to - , the attenuation is discontinued and returned to att level by the same cycle. the soft mute is effective for changing the signal source without stopping the signal transmission. smute bit attenuation dzf1,2 att level - aout 8192/fs gd gd (1) (2) (3) (4) (1) notes: (1) att_data att transition time ( table 13 ). for example, in normal speed mode, this time is 1792lrck cycles (1792/fs) at att_data=00h. att transition of the soft-mute is from 00h to 7fh (2) the analog output corresponding to the digital input has group delay. (gd) (3) if the soft mute is cancelled before attenuating to - , the attenuation is discontinued and returned to att level by the same cycle. (4) when the input data at all the channels of the group are continuously zeros for 8192 lrck cycles, the dzf pin of each channel becomes ?h?. the dzf pin i mmediately returns to ?l? if the input data of eith er channel of the group are not zero. figure 15. soft mute and zero detection system reset the ak4627 should be reset once by bringing the pdn pin = ?l? upon power-up. the ak4627 is powered up and the internal timing starts clocking by lrck ? ? after exiting reset and power down state by mclk. the ak4627 is in the power-down mode until mclk and lrck are input.
[ak4627] ms1278-e-02 2012/03 - 26 - power-down the adc and dacs of ak4627 are placed in the power-down mode by bringing th e pdn ?l? and both digital filters are reset at the same time. bringing the pdn pin=?l? also rese ts the control registers to their default values. in the power-down mode, the analog outputs become to vcom voltage and dzf1-2 pins output ?l?. this reset should always be made after power-up. in case of adc, an analog initialization cycle star ts after exiting th e power-down mode. therefore, the output data, sdto1-2 become available after 516 cycles of lrck clock. in case of the dac, an analog initialization cycle starts after exiting the power-down mode. the analog outputs are vcom voltage during the initialization. figure 16 shows the power-down/up sequences. all adcs and all dacs can be powered-down by pwadn and pwdan bits respectively. dac1-3 can be power-down individually by pdda1-3 bits. in this case, the internal re gister values are not initialized. when pwadn bit= ?0? and pdad1-2 bits = ?0?, sdto1-2 become ?l?. when pwdan bit = ?0? and pdda1-3 bits= ?0?, the analog outputs go to vcom voltage and dzf1-2 pins go to ?h?. as some click nois e occurs, the analog output should be muted externally if the click noise influences system applications. a dc internal state pdn 516/ fs normal operation power-down i nit cycle normal operation (1 ) don?t care g d gd clock in mclk,lr ck,sclk a dc in (analog) ?0?data a dc ou t (digital) normal operation power-down normal operat ion dac internal state ?0?data dac in (digital) dac out (analog) gd external mute mute on gd (3) (3 ) (4) (5) (6) (6) (9) 512/fs init cycle (2) dzf1/dzf2 (7) (8 ) 10 11/fs (10) notes: (1) the analog part of adc is initiali zed after exiting the power-down state. (2) the analog part of dac is initiali zed after exiting the power-down state. (3) digital outputs corresponding to analog inputs and analog outputs corresponding to digital inputs have group delay (gd). (4) adc outputs ?0? data in power-down state. (5) click noise occurs at the end of initialization of the analog part. mute the digital output externally if the click noise influences system application. (6) click noise occurs at the falling edge of pdn and at 512/fs after the rising edge of pdn. (7) when the external clocks (mclk, bick and lrck) are stopped, the ak4627 should be in the power-down mode. (8) dzf pins are ?l? in power-down mode (pdn pin= ?l?). (9) mute the analog output externally if the click noise (6) influences system application. (10) dzf1-2 pins are ?l? for 10 11/fs after pdn = ? ?. figure 16. power-down/up sequence example
[ak4627] ms1278-e-02 2012/03 - 27 - reset function (1) reset by rstn bit when rstn bit = ?0?, adc and dacs are powered-down but the internal registers are not initialized. the analog outputs go to vcom voltage, dzf1-2 pins output ?h? and the sdto1-2 pins outputs ?l?. as some click noise occurs, the analog output should be muted externally if the click noise influences system application. figure 17 shows the power-up sequence. a dc internal state rstn bit normal operation digital block power-down normal operation don?t care gd gd clock in mclk,lrck,sclk a dc in (analog) ?0?data a dc out (digital) normal operation normal operation dac internal state ?0?data dac in (digital) dac out (analog) gd gd (2) (2) (3) (4) (6) (6) dzf1/dzf2 (7) internal rstn bit digital block power-down 1~2/fs (9) 4~5/fs (9) 4 5/fs (8) (5) 516/fs init cycle (1) notes: (1) the analog part of the adc is initialized after exiting reset state. (2) digital outputs corresponding to analog inputs and analog outputs corresponding to digital inputs have group delay (gd). (3) adc outputs ?0? data in power-down state. (4) click noise occurs when the internal rstn bit becomes ?1?. mute the digital output externally if the click noise influences system application. (5) the analog outputs become vcom voltage. (6) click noise occurs at 4 5/fs after rstn bit becomes ?0?, and occurs at 1 2/fs after rstn bit becomes ?1?. this noise is output even if ?0? data is input. (7) the external clocks (mclk, bick and lrck) can be stopped in reset mode. when exiting reset mode, ?1? should be written to rstn bit after the external clocks (mclk, bick and lrck) are fed. (8) the dzf pins go to ?h? when the rstn bit becomes ?0?, and go to ?l? at 6~7/fs after rstn bit becomes ?1?. (9) there is a delay, 4~5/fs from rstn bit ?0? to the internal rstn bit ?0?. figure 17. reset sequence example
[ak4627] ms1278-e-02 2012/03 - 28 - (2) reset by mclk, lrck or bick stop the ak4627 is automatically placed in reset state when mclk, lrck or bick is stopped during normal operation (rstn pin = ?h?). in this reset state, the analog output becomes vcom voltage, and sdto1-2, dzf1-2 pins output ?l?, but register values are not initialized. when mclk, lrck or bick are input again, the ak4627 is powered up. after exiting reset following power-up, the adc enters initializing cycl e. therefore, sdto1-2 output da ta is not stable in 516x lrck cycle. after exiting reset following power-up, the dac enters initializing cycle. the analog output becomes vcom voltage during this initializing cycle. figure 19 shows the reset sequence by clock stop. a dc internal state rstn bit 516/fs normal operation power-down init cycle normal operation (1) gd gd a dc in (analog) ?0?data a dc out (digital) normal operation power-down normal operation dac internal state ?0?data dac in (digital) dac out (analog) gd external mute mute on gd (3) (3) (4) (5) (6) (6) (8) 512/fs init cycle (2) dzf1/dzf2 (7) 10 11/fs (10) clock in mclk, bick, lrck clk stop notes: (1) the analog section of the adc is initialized after exiting reset state. (2) the analog section of the dac is initialized after exiting reset state. (3) the digital output corresponding to a specific analog input, and the analog ouput corresponding to a specific digital input have group delay (gd). (4) adc output is ?0? data during reset. (5) click noise occurs at the end of initilizing cycle of the adc. mute the digital output if click noise influences systemapplications. (6) click noise occurs within 20usec from mclk, lrck or bick stop/start. (7) dzf1-2 pins output ?l? during reset. (8) mute the analog output externally if click noise (6) influences system applications. figure 18. reset 2 sequence example
[ak4627] ms1278-e-02 2012/03 - 29 - adc partial power-down function all of the adcs can be powered-down individually by pdad2-1 bits. the analog part and the digital part of the adc are in power-down mode when the pdad2-1 bits = ?1?. the analog section of adcs are initialized after exiting the power-down state. digital outputs corresponding to analog inputs have group delay (gd). adc outputs ?0? data in power-down state. click noise occurs when the internal rstn bit becomes ?1?. mute the digital output externally if the click noise influences system applications. figure 19 shows the power-down and power-up sequences by pdad2-1 bits. pdad2-1 bit a dcdigital internal state normal operation a dc analog internal state power-down clock in mcl k, lrc k, sc lk normal operation channel power-down normal operation power down channel normal operat ion power-down power-down normal operat ion init cycle normal operation 516/fs (1) init cycle normal operation 516/fs (1) gd gd a dc in (analog) ?0?dat a a dc out (digital) (2 ) (3) (4) (4) (2) gd gd a dc in (analog) ?0?data a dc ou t (digital) (3) (2 ) (2 ) note: (1) the analog part of the adc is initialized after exiting reset state. (2) analog outputs corresponding to the digital inputs have group delay (gd). (3) adc outputs ?0? data in power-down state. (4) click noise occurs when the internal rstn bit becomes ?1 ?. mute the digital output externally if the click noise influences system applications. figure 19. adc partial power-down example
[ak4627] ms1278-e-02 2012/03 - 30 - dac partial power-down function all dacs of ak4627 can be powered-down individually by pdda1-3 bits. the analog part of dac is in power-down mode by pdda1-3 bits = ?1?, however, the digital part is not powered-down. even if all dacs were set in power-down mode by the partial power-down bits, the digital part con tinues an operation. the analog output channels which are powered-down by pdda1-3 bits are fixed to the vcom voltage. although dzf detection is in operation, dzf detection results of these analog output channels are not reflected to dzf1-2 pins. some click noise occurs in both set-up and release of power-down. mute the analog output externally or set pdda1-3 bits when pwdan bit = ?0? or rstn bit = ?0?, if click noise aversely affects system performance. figure 20 shows the power-down/up sequences by pdda1-3 bits. pdda1-3 bit dzf1/dzf2 8192 /fs ?0?data dac in (digital) dac out (analog) gd gd (1 ) (3) (3) (2 ) dac digital internal state normal operation normal operation dac analog internal state power-down normal operation clock in mclk,lrck,sclk dac in (digital) dac out (analog) normal operation channel (4) (5) gd 8192/fs gd power-down normal operation normal operation (2 ) (3) (3) (4) power down channel dzf detect internal state dzf detect internal state ?0?data (6 ) notes: (1) digital outputs corresponding to analog inputs and analog outputs corresponding to digital inputs have group delay (gd). (2) analog outputs of the dac when powered down by pdda1-3 bits = ?1? are fixed to the vcom voltage. (3) immediately after pdda1-3 bits are changed, a click noise occurs at the output of the channel which is changed by the own pdda bits. (4) although dzf detection is in operation, dzf detection results of powered-down dac analog output channels are not reflected to dzf1-2 pins. (5) dzf detection of the dac which is in power-down mode is ignored, and dzf1-2 pins become ?h?. (6) when signal is input to a dac, even if other dacs are powered-down by partial power-down by pdda bits, dxf1-2 pins do not become ?h?. mute the analog output externally if the click noise influences system applications. figure 20. dac partial power-down example
[ak4627] ms1278-e-02 2012/03 - 31 - serial control interface the ak4627?s functions are controlled through registers. the registers may be written by two types of control modes. the chip address is determined by the state of the cad0 an d cad1 inputs. the pdn pin = ?l? initializes the registers to their default values. writing ?0? to the rstn bit can initialize th e internal timing circuit but the register data will not be initialized. when the ps pin state is changed, the ak4627 should be reset by the pdn pin. * writing to control register is invalid when the pdn pin = ?l?. (1) 3-wire serial control mode (i2c pin= ?l?) internal registers may be written thro ugh the 3 wire p interface pins (csn , cclk and cdti). the data on this interface consists of chip address (2b its, cad0/1), read/write (1bit, fixed to ?1?, write only), register address (msb first, 5bits) and control data (msb first, 8bits). ad dress and data is clocked in on the rising edge of cclk and data is clocked out on the falling edge. for write opera tions, data is latched after a low-to-high transition of csn. the clock speed of cclk is 5mhz(max). * the ak4627 does not support read commands in 3wire serial control mode. cdti cclk csn c1 0 1234567 8 9 10 11 12 13 14 15 d4 d5 d6 d7 a1 a2 a3 a4 r/w c0 a0 d0 d1 d2 d3 c1-c0: chip address (c1=cad1, c0=cad0) r/w: read/write (fixed to ?1?, write only) a4-a0: register address d7-d0: control data figure 21. 3-wire seri al control i/f timing
[ak4627] ms1278-e-02 2012/03 - 32 - (2) i 2 c-bus control mode (i2c pin= ?h?) the ak4627 supports the fast-mode i 2 c-bus (max: 400khz). 1. write operations figure 22 shows the data transfer sequence in i 2 c-bus mode. all commands are preceded by a start condition. a high to low transition on the sda line while scl is high indicates a start condition ( figure 28 ). after the start condition, a slave address is sent. this address is 7 bits long followed by the eighth bit which is a data direction bit (r/w) ( figure 23 ). the most significant five bits of the slave address are fixed as ?00100?. the next two bits are cad1 and cad0 (device address bits). thes e two bits identify the specific device on the bus. the hard-wired input pins (cad1 pin and cad0 pin) set these device address bits. if the slave address matches that of the ak4627, the ak4627 generates an acknowledge and the op eration is executed. r/w bit = ?1? indicates that the read operation is to be executed. ?0? indicates that the write operation is to be executed. the second byte consists of the address for control registers of the ak4627. the format is msb first, and those most significant 3-bits are fixed to zeros ( figure 24 ). those data after the second byte contain control data. the format is msb first, 8bits ( figure 25 ). the ak4627 generates an acknowledge af ter each byte has been received. a data transfer is always terminated by a stop condition genera ted by the master. a low to high transition on the sda line while scl is high defines a stop condition ( figure 28 ). the ak4627 is capable of more than one byte write operati on by one sequence. after receipt of the third byte, the ak4627 generates an acknowledge, and awaits the next da ta again. the master can transmit more than one byte instead of terminating the write cycle afte r the first data byte is transferred. af ter the receipt of eac h data, the internal 5bits address counter is incremented by one, and the next da ta is taken into next address automatically. if the address exceed 0dh prior to generating a stop co ndition, the address counter will ?roll over? to 00h and the previous data will be overwritten. the data on the sda line must be stable during the high period of the clock. the high or low state of the data line can only be changed when the clock signal on the scl line is low ( figure 30 ) except for the start and the stop condition. sda s t a r t a c k a c k s slave a ddress a c k sub a ddress(n) data(n) p s t o p data(n+x) a c k data(n+1) a c k r/w a c k figure 22. data transfer sequence at the i 2 c-bus mode 0 0 1 0 0 cad1 cad0 r/w (those cad1/0 should match with cad1/0 pins) figure 23. the first byte 0 0 0 a4 a3 a2 a1 a0 figure 24. the second byte d7 d6 d5 d4 d3 d2 d1 d0 figure 25. byte structure after the second byte
[ak4627] ms1278-e-02 2012/03 - 33 - 2. read operations set the r/w bit = ?1? for the read opera tion of the ak4627. after transmission of data, the master can read the next address?s data by generating an acknowledg e instead of terminating the write cycle af ter the receipt of the first data word. after receiving each data packet the internal 6-bit address counter is incremented by one, and the next data is automatically taken into the next address. if the addre ss exceeds 16h prior to generating stop condition, the address counter will ?roll over? to 00h and th e data of 00h will be read out. the ak4627 supports two basic read operations: current address read and random address read. 2-1. current address read the ak4627 contains an internal address counter that maintains the address of the last word accessed, incremented by one. therefore, if the last access (either a read or write) was to address ?n?, the next current read operation would access data from the address ?n+1?. afte r receipt of the slave address with r/w bit ?1?, the ak4627 generates an acknowledge, transmits 1-byte of data to the address set by the internal address counter and increments the internal address counter by 1. if the master does not generate an acknowledge but generates a stop condition instead, the ak4627 ceases transmission. sda slave address s s t a r t r/w="1" a c k a c k data(n+1) a c k data(n+2) a c k a c k data(n+x) a c k p s t o p data(n) figure 26. current address read 2-2. random address read the random read operation allows the master to access any memo ry location at random. prior to issuing a slave address with the r/w bit =?1?, the master must ex ecute a ?dummy? write operatio n first. the master issues a start request, a slave address (r/w bit = ?0?) and then the register address to read. after the register addres s is acknowledged , the master immediately reissues the start request and the slave address with the r/w bit =?1?. the ak4627 then generates an acknowledge, 1 byte of data and increments the internal address counter by 1. if the master does not generate an acknowledge but generates a stop condition instead, the ak4627 ceases transmission. sda slave address s s t a r t r/w="0" a c k a c k a c k data(n) a c k data(n+x) a c k p s t o p sub address(n) s slave address r/w="1" s t a r t data(n+1) a c k a c k figure 27. random address read
[ak4627] ms1278-e-02 2012/03 - 34 - scl sda stop condition start condition s p figure 28. start and stop conditions scl from master acknowledge data output by master data output by slave(ak4529) 1 9 8 start condition not acknowledge clock pulse for acknowledgement s 2 figure 29. acknowledge on the i 2 c-bus scl sda data line stable; data valid change of data allowed figure 30. bit transfer on the i 2 c-bus
[ak4627] ms1278-e-02 2012/03 - 35 - mapping of program registers addr register name d7 d6 d5 d4 d3 d2 d1 d0 00h control 1 0 0 tdm1 tdm0 dif1 dif0 0 smute 01h control 2 0 dfs1 loop1 loop0 0 dfs0 acks 0 02h lout1 volume control att7 att6 att5 att4 att3 att2 att1 att0 03h rout1 volume control att7 att6 att5 att4 att3 att2 att1 att0 04h lout2 volume control att7 att6 att5 att4 att3 att2 att1 att0 05h rout2 volume control att7 att6 att5 att4 att3 att2 att1 att0 06h lout3 volume control att7 att6 att5 att4 att3 att2 att1 att0 07h rout3 volume control att7 att6 att5 att4 att3 att2 att1 att0 08h de-emphasis 0 1 dema1 dema0 demb1 demb0 demc1 demc0 09h att speed & power down control 0 0 ats1 ats0 pdda3 pdda2 pdda1 rstn 0ah zero detect 0 dzfm3 dzfm2 dzfm1 dzfm0 pwvrn pwadn pwdan 0dh power down control 0 0 0 0 0 0 pdad2 pdad1 note: for addresses 0bh, 0ch, 0eh and 0fh, data must not be written. when the pdn goes to ?l?, the register s are initialized to their default values. when rstn bit goes to ?0?, the internal timing is reset an d dzf1-2 pins go to ?h?, but registers are not initialized to their default values. smute and dfs0 bits are ored with pins.
[ak4627] ms1278-e-02 2012/03 - 36 - register definitions addr register name d7 d6 d5 d4 d3 d2 d1 d0 00h control 1 0 0 tdm1 tdm0 dif1 dif0 0 smute default 0 0 0 0 1 0 0 0 smute: soft mute enable 0: normal operation 1: all dac outputs soft-muted register bit of smute is ored with the smute pin when the ps pin= ?l?. dif1-0: audio data interface modes ( table 8 , table 9 , table 10 ) initial: ?10?, mode 2 tdm1-0: tdm format select ( table 8 , table 9 , table 10 ) mode tdm1 tdm0 data output pins data input pins sampling speed 0 0 0 sdto1-2 sdti1-3 normal, double, quad speed 1 0 1 sdto1 sdti1 normal speed 2 1 0 - - n/a 3 1 1 sdto1 sdti1-2 normal, double speed (n/a: not available)
[ak4627] ms1278-e-02 2012/03 - 37 - addr register name d7 d6 d5 d4 d3 d2 d1 d0 01h control 2 0 dfs1 loop1 loop0 0 dfs0 acks 0 default 0 0 0 0 0 0 0 0 acks: master clock frequency auto setting mode enable 0: disable, manual setting mode 1: enable, auto setting mode master clock frequency is detected automatically at ac ks bit ?1?. in this case, the settings of dfs bits are ignored. when this bit is ?0?, dfs0 and dfs1 bits set the sampling speed mode. dfs1-0: sampling speed mode ( table 1 ) register bit of dfs0 is ored with dfs0 pin when the ps pin= ?l?. the settings of dfs bits are ignored at acks bit ?1?. loop1-0: loopback mode enable 00: normal (no loop back) 01: lin1 lout1, lout2, lout3 rin1 rout1, rout2, rout3 the digital adc output is connected to the digital dac input. in this mode, the input dac data to sdti1-3 is ignored. in loopback mode, the actual audio format is forced to mode2 when the sdto audio format setting is for mode0/1/2, and the actual audio format is forced to mode3 when the setting is for mode3. ( table 8 ) 10: sdti1(l) sdti2(l), sdti3(l) sdti1(r) sdti2(r), sdti3(r) in this mode the input dac data to sdti2-3 is ignored. 11: lin2 lout1, lout2, lout3 rin2 rout1, rout2, rout3 the digital adc output is connected to the digital dac input. in this mode, the input dac data to sdti1-3 is ignored. in loopback mode, the actual audio format is forced to mode2 when the sdto audio format setting is for mode0/1/2, and the actual audio format is forced to mode3 when the setting is for mode3. ( table 8 )
[ak4627] ms1278-e-02 2012/03 - 38 - addr register name d7 d6 d5 d4 d3 d2 d1 d0 02h lout1 volume control att7 att6 att5 att4 att3 att2 att1 att0 03h rout1 volume control att7 att6 att5 att4 att3 att2 att1 att0 04h lout2 volume control att7 att6 att5 att4 att3 att2 att1 att0 05h rout2 volume control att7 att6 att5 att4 att3 att2 att1 att0 06h lout3 volume control att7 att6 att5 att4 att3 att2 att1 att0 07h rout3 volume control att7 att6 att5 att4 att3 att2 att1 att0 default 0 0 0 0 0 0 0 0 att7-0: attenuation level ( table 12 ) addr register name d7 d6 d5 d4 d3 d2 d1 d0 08h de-emphasis 0 1 dema1 dema0 demb1 demb0 demc1 demc0 default 0 1 0 1 0 1 0 1 dema1-0: de-emphasis response control for dac1 data on sdti1 ( table 7 ) initial: ?01?, off demb1-0: de-emphasis response control for dac2 data on sdti2 ( table 7 ) initial: ?01?, off demc1-0: de-emphasis response control for dac3 data on sdti3 ( table 7 ) initial: ?01?, off
[ak4627] ms1278-e-02 2012/03 - 39 - addr register name d7 d6 d5 d4 d3 d2 d1 d0 09h att speed & power down control 0 0 ats1 ats0 pdda3 pdda2 pdda1 rstn default 0 0 0 0 0 0 0 1 rstn: internal timing reset 0: reset. dzf1-2 pins go to ?h?, but registers are not initialized. 1: normal operation ats1-0: digital attenuator transition time setting ( table 13 ) initial: ?00?, mode 0 pdda3-1: power-down control (0: power-up, 1: power-down) pdda1: power down control of dac1 pdda2: power down control of dac2 pdda3: power down control of dac3 addr register name d7 d6 d5 d4 d3 d2 d1 d0 0ah zero detect 0 dzfm3 dzfm2 dzfm1 dzfm0 pwvrn pwadn pwdan default 0 0 1 1 1 1 1 1 pwdan: power-down control of dac1-3 0: power-down 1: normal operation pwadn: power-down control of adc 0: power-down 1: normal operation pwvrn: power-down control of reference voltage 0: power-down 1: normal operation dzfm3-0: zero detect mode select ( table 11 ) initial: ?0111?, disable addr register name d7 d6 d5 d4 d3 d2 d1 d0 0dh power down control 0 0 0 0 0 0 pdad2 pdad1 default 0 0 0 0 0 0 0 0 pdad2-1: power-down control (0: power-up, 1: power-down) pdad1: power down control of adc1 pdad2: power down control of adc2
[ak4627] ms1278-e-02 2012/03 - 40 - system design figure 31 shows the system connection diagram. an evaluation board is available which demonstrates application circuits, the optimum layout, power supply arrangements and measurement results. condition: tvdd=5v, 3-wire serial control mode, cad1-0 = ?00? + 0.1u 0.1u 2.2u + 5 up analog 5v + 10u dsp audio (dir) digital audio source 0.1u 10u power-down control ak4627 38 37 40 39 41 43 42 44 45 47 46 48 23 24 21 22 20 18 19 17 16 14 15 13 1 2 3 4 5 6 7 8 9 10 11 12 36 35 34 33 32 31 30 29 28 27 26 25 mclk cad0 cad1 ps sdto1 sdto2 tvdd dvdd vss1 tdm0/sda/cdti dif1/scl/cclk dif0/csn pdn bick lrck sdti1 sdti2 sdti3 tst3 dfs0 i2c/tst6 tst2 tst4 tst5 dzf2 dzf1 vss2 avdd vrefh vcom rout1 lout1 rout2 lout2 rout3 lout3 rin2- rin2+/rin2 lin2- lin2+/lin2 rin1- rin1+/rin1 lin1- lin1+/lin1 tst1 sgl dzfe smute mute mute mute mute mute mute 2.2u analog ground digital ground figure 31. typical connection diagram
[ak4627] ms1278-e-02 2012/03 - 41 - analog ground digital ground system controller cad0 1 2 3 4 5 6 7 8 9 11 10 cad1 sdto1 sdto2 tvdd dvdd vss1 tdm0/sda/cdti dif1/scl/cclk dif0/csn vss2 lin2+/lin2 lin2- mclk dzf1 13 14 15 16 1 8 19 20 21 22 23 sdti1 bick lrck sdti2 tst3 dfs0 i2c/tst6 tst2 tst4 a vdd vrefh vcom rout1 lout1 rout2 lout2 rout3 lout3 ak4627 s dti 3 p/s 35 3 4 33 32 31 30 29 28 27 25 26 47 46 45 44 43 42 41 40 39 38 37 pdn 12 24 tst5 dzf2 36 48 rin2+/rin2 rin2- rin1+/rin1 rin1- lin1+/lin1 lin1- tst1 sgl dzfe smute 17 figure 32. ground layout note: vss1 and vss2 must be connected to the same anal og ground plane. 1. grounding and power supply decoupling the ak4627 requires careful attention to power supply and grounding arrangements. avdd and dvdd are usually supplied from analog supply in system. alternatively if avdd and dvdd are supplied separately, the power up sequence is not critical. vss1 and vss2 of the ak4627 must be connected to analog ground plane. system analog ground and digital ground should be connected together near to where the supplies are brought onto the printed circuit board. decoupling capacitors should be as near to the ak462 7 as possible, with the sma ll value ceramic capacitor being the nearest. 2. voltage reference inputs the voltage of vrefh sets the analog input/output range. the vrefh pin is normally connected to the avdd pin with a 0.1f ceramic capacitor in between the vs s2 pin. vcom is a signal ground of this chip. a 2.2f electrolytic capacitor in parallel with a 0.1f ceramic capacitor attached to betwee n the vcom and vss2 pins elim inates the effects of high frequency noise. no load current may be drawn from the vcom pin. all signals, especially clocks, should be kept away from the vrefh and vcom pins in order to avoid unwanted coupling into the ak4627. 3. analog inputs the adc inputs correspond to single-ended and differential wh ich able to select by the sgl pin. when the inputs are single-ended, the signal is internally biased to the common voltage (avdd1x1/2) with 14k (typ) resistance. the input signal range scales with the supply voltage and nominally 0.68xvrefh vpp (typ) @fs=48khz. when the inputs are differential, the signal is internally bias ed to the common voltage (avdd2x1/2) with 32k (typ) resistance. the input signal range between lin(rin)+ and lin(rin) ? scales with the supply voltage and nominally 0.68xvrefh vpp (typ) @fs=48khz .the adc output data format is 2?s complement. the internal hpf removes the dc offset. the ak4627 samples the analog inputs at 64fs. the digital filte r rejects noise above the stop band except for multiples of the sampling frequency of analog inputs. the ak4627 includes an anti-aliasing filter (rc filter) to attenuate a noise around the sampling frequency of analog inputs.
[ak4627] ms1278-e-02 2012/03 - 42 - 4. analog outputs the analog outputs are also single-ended and centered around the vcom voltage. the input signal range scales with the supply voltage and nominally 0.6 x vrefh vpp. the dac input data format is 2?s complement. the output voltage is a positive full scale for 7fffffh(@24bit) and a negative full scale for 800000h(@24bit). the ideal output is vcom voltage for 000000h(@24bit). the internal analog filters re move most of the noise generated by the delta-sigma modulator of dac beyond the audio passband. dc offsets on analog outputs are eliminated by ac coupling since dac outputs have dc offsets of a few mv. 5. external analog inputs circuit figure 33 shows the input buffer circuit example 3. the input level of this circuit is 3.4vpp. analog in analog in 3.4vpp 3.4vpp 2.2uf ain+ ain- ak4627 + - 50% + - 50% 2.2uf figure 33. input buffer circuit example 1 (ac coupled differential input) figure 34 shows the input buffer circuit example 3. th e input level of this circuit is 3.4vpp. analog in 3.4vpp ain+ ain- ak4627 open + - 50% 2.2uf figure 34. input buffer circuit example 2 (ac coupled single-ended input)
[ak4627] ms1278-e-02 2012/03 - 43 - 6. peripheral i/f example the ak4627 supports signals fr om external devices which are operated on 3.3v power supplies for ttl inputs. the power supply for output buffer (tvdd) should be 3.3v when those external devices are connected. figure 35 shows an i/f example when 3.3v and 5v power supply devices are used. 3.3v analog 5v analog 3.3v digital 5v digital pll i/f audio signal dsp ak4113 an alo g digital control signal up & others ak4627 5v for input 3.3v for output figure 35. power supply connection example
[ak4627] ms1278-e-02 2012/03 - 44 - package 1 12 48 13 7.0 9.0 7.0 9.0 0.22 0.08 48pin lqfp(unit: mm) 0.10 37 24 25 36 0.09 0.20 1.40 0.05 0.13 0.13 1.70max 0 10 0.10 0.30 ~ 0.75 0.5 s s m package & lead frame material package molding compound: epoxy lead frame material: cu lead frame surface treatment: solder (pb free) plate
[ak4627] ms1278-e-02 2012/03 - 45 - marking AK4627VQ xxxxxxx 1 1) pin #1 indication 2) date code: xxxxxxx(7 digits) 3) marking code: AK4627VQ 4) asahi kasei logo date ( yy/mm/dd ) revision reason page contents 11/01/26 00 first edition 11/08/29 01 specification change 7 analog characteristics adc analog input characteris tics (single-ended inputs) s/(n+d), fs=48khz: 92 96db (typ) fs=96khz: 86 92db (typ) dr, fs=96khz: 96 99db (typ) fs=96khz, a-weighted: 102 105db (typ) s/n: fs=96khz: 96 99db (typ) fs=96khz, a-wieghted: 102 105db (typ) adc analog input characteristics (differential inputs) s/(n+d), fs=48khz: 92 96db (typ) fs=96khz: 86 94db (typ) dr, fs=96khz: 97 100db (typ) fs=96khz, a-weighted: 103 106db (typ) s/n: fs=96khz: 97 100db (typ) fs=96khz, a-wieghted: 103 106db (typ) 8 dac analog output characteristics s/(n+d), fs=48khz: 90 98db (typ) fs=96khz: 88 98db (typ) fs=192khz: 88 98db (typ) revision history
[ak4627] ms1278-e-02 2012/03 - 46 - date ( y/m/d ) revision reason page contents 12/03/07 02 error correction 3 ordering guide ak4627 AK4627VQ 9 dc characteristics high-level output voltage condition: sdto1-2, lrck, bick pins sdto1-2 pins low-level output voltage condition: sdto1-2, lrck, bick, dzf1, dzf2 pins sdto1-2, dzf1, dzf2 pins important notice z these products and their specifications ar e subject to change without notice. when you consider any use or application of these produc ts, please make inquiries the sales office of asahi kasei microdevices corporation (akm) or authorized distributors as to current status of the products. z descriptions of external circuits, application circuits, software and other related information contained in this document are provided only to illustrate the operation and application examples of the semiconductor products. you are fully responsible for the incorporatio n of these external circuits, application circuits, software and other related information in the design of your equipments. akm assumes no responsibility for any losses incurred by you or third parties arising from the use of these information herein . akm assumes no liability for infringement of any patent, intellectual property, or other rights in the application or use of such information contained herein. z any export of these products, or devices or systems containing them, may require an export license or other official approval under the law and regulations of the country of export pertaining to customs and tariffs, currency exchange, or strategic materials. z akm products are neither intended nor auth orized for use as critical components note1 ) in any safety, life support, or other hazard related device or system note2 ) , and akm assumes no responsibility for such use, except for the use approved with the express written consent by representative director of akm. as used here: note1 ) a critical component is one whose failure to function or perform may reasonably be expected to result, whether directly or indirectly, in the loss of the safety or effectiveness of the device or system containing it, and which must therefore meet very high standards of performance and reliability. note2 ) a hazard related device or system is one designed or intended for life support or maintenance of safety or for applications in medicine, aerospace, nuclear energy, or other fields, in which its failure to function or perform may reasonably be expected to result in loss of life or in significant injury or damage to person or property. z it is the responsibility of the buyer or distributor of akm products, who distri butes, disposes of, or otherwise places the product with a third party, to notify such third party in advance of the above content and conditions, and the buyer or distributor agrees to assume any and all responsibility and liability for and hold akm harmless from any and all claims arising from the use of said product in the absence of such notification.

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